Updated on 2024/04/08

写真a

 
TADA Jubee
 
Title
Associate Professor

Research Areas

  • Informatics / Computer system

Graduating School

  • Tohoku University, Faculty of Engineering, Department of Mechanical and Intelligent Engineering

    1998.03, Graduated

Graduate School

  • Tohoku University, Graduate School, Division of Information Science, Computer and Mathematical Sciences

    Doctor's Course, 2003.03, Completed

Degree

  • Ph.D, Tohoku University, 2003.03

 

Papers

  • An Interleaved Multiple-Hit Cache for Simultaneous Multithreaded VLIW Processors, Proceedings of the Third International Conference on Parallel and Distributed Computing, Applications and Technologies, 25-32, 2002.09

    Jubei Tada, Hugo Kenji Pereira Harada, Kentaro Sano, Hiroaki Kobayashi, Tadao Nakamura

    Multiple Authorship (Only Japanese)

  • An Instruction Cache Mechanism for Simultaneous Multithreaded VLIW Processors, International Journal of Asian Information-Science-Life, 2(1) 45-55, 2003.01

    Jubei Tada, Hugo Kenji Pereira Harada, Kentaro Sano, Hiroaki Kobayashi, Tadao Nakamura

    Multiple Authorship (Only Japanese)

  • A Sophisticated Multiplier in Advanced CMOS Technologies, Proceedings of The 21st International Technical Conference on Circuits/Systems, Computers and Communications, 53-56, 2006.07

    Ryusuke Egawa, Jubei Tada, Tadao Nakamura, Gensuke Goto

    Multiple Authorship (Only Japanese)

  • Future Design Strategy of Combinational Logic Circuits, Proceedings of The Fourth International Conference on Information, the Fourth Irish Conference on the Mathematical Foundations of Computer Science and Information Technology'06, 110-113, 2006.08

    Ryusuke Egawa, Tasuku Ito, Tomoyuki Inoue, Jubei Tada, Ken-ichi Suzuki,Tadao Nakamura

    Multiple Authorship (Only Japanese)

  • Gain-based Delay Balancing Technique for Wave Pipelining, ITC-CSCC 2007, 451-452, 2007.07

    Jubee Tada, Ryusuke Egawa, Keiichiro Sano, Gensuke Goto, Tadao Nakamura

    Multiple Authorship (Only Japanese)

  • Scaling Effects in Combinational Logic Circuit Design, Information, 10(5) 695-702, 2007.09

    Ryusuke Egawa, Tasuku Itoh, Tomoyuki Inoue, Ken-ichi Suzuki, Tadao Nakamura, Jubei Tada

    Multiple Authorship (Only Japanese)

  • Parallel Image Reconstruction Operation by Dedicated Hardware for Three Dimensional Ultrasound Imaging, IEEE UFFC, 1522-1525, 2007.11

    Keiichi Satoh,Jubei Tada, Hirotaka Yanagida, Yasutaka Tamura

    Multiple Authorship (Only Japanese)

  • Complex Multiplier Suited for FPGA Structure, Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2008), 341-344, 2008.07

    Keiichi Satoh, Jubee Tada, Kenta Yamaguchi, and Yasutaka Tamura

    Multiple Authorship (Only Japanese)

  • Gain Based Delay Balancing in the Deep Submicron Era, Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2008), 577-580, 2008.07

    Ryusuke Egawa, Jubee Tada, Hiroaki Kobayashi, and Gensuke Goto

    Multiple Authorship (Only Japanese)

  • Three-dimensional ultrasonic imaging operation using FPGA, IEICE Electronics Express (ELEX), 6(2) 84-89, 2009.01

    Keiichi Satoh, Jubee Tada, and Yasutaka Tamura

    Multiple Authorship (Only Japanese)

  • Evaluation of Fine Grain 3-D Integrated Arithmetic Units, IEEE International Conference on 3D System Integration (3D IC), 2009.09

    Ryusuke Egawa, Jubee Tada, Hiroaki Kobayashi, Gensuke Goto

    Multiple Authorship (Only Japanese)

  • Edge-Connected, Crossed-electrode Array Comprising Non-linear Transducers, 2009 IEEE International Ultrasonics Symposium, 2221-2224, 2009.09

    Ichiro Fujishima, Yasutaka Tamura, Hirotaka Yanagida, Jubee Tada, Tatsuhisa Takahashi

    Multiple Authorship (Only Japanese)

  • Complex multiplier suited for FPGA structure, Journal of Communication and Computer, 6(12) 55-62, 2009.12

    Keiichi Satoh, Jubee Tada, Yasutaka Tamura, Gensuke Goto

    Multiple Authorship (Only Japanese)

  • A Middle-Grain Circuit Partitioning Strategy for 3-D Integrated Floating-Point Multipliers, IEEE International Conference on 3D System Integration (3D IC), 2012.01

    Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto

    Multiple Authorship (Only Japanese)

  • Designing a 3D Stacked Vector Cache, Design, Automation & Test in Europe 2012 (DATE12), 2012.03

    Ryusuke Egawa, Yusuke Endo, Jubei Tada, Hiroyuki Takizawa, Hiroaki Kobayashi, Gensuke Goto

    Multiple Authorship (Only Japanese)

  • A Cache Replacement Algorithm Based on Dynamic Loop Detection, Proceedings of the 27th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2012), 2012.07

    Jubee Tada, Akihisa Abe

    Multiple Authorship (Only Japanese)

  • Exploring Design Space of a 3D Stacked Vector Cache, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC12), 2012.11

    Ryusuke EGAWA, Yusuke Endo, Jubee Tada, Hiroyuki Takizawa, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • Exploring a Design Space of 3-D Stacked Vector Processors, Sustained Simulation Performance 2012, 35-49, 2012.10

    Ryusuke Egawa, Jubee Tada, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • Performance Evaluation of 3D Stacked 32-bit Parallel Multipliers, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2013), 57-62, 2013.06

    Jubee Tada

    Multiple Authorship (Only Japanese)

  • Power and Performance Evaluation of 3-D Stacked Floating-point Multipliers, 2013 IEEE Computer Society Annual Symposium on VLSI, 218-223, 2013.08

    Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • Design of a 3-D Stacked Floating-Point Adder, IEEE International Conference on 3D System Integration (3DIC2013), 2013.10

    Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • Vertically Integrated Processor and Memory Module Design for Vector Supercomputers, IEEE International Conference on 3D System Integration (3DIC2013), 2013.10

    Ryusuke Egawa, Masayuki Sato, Jubee Tada, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • Performance evaluation of 3-D stacked 32-bit parallel multipliers, ACM SIGARCH Computer Architecture News, 41(5) 89-94, 2013.12

    Jubee Tada

    Single Author

  • An Impact of Circuit Scale on the Performance of 3-D Stacked Arithmetic Units, IEEE International Conference on 3D System Integration (3DIC2014), 2014.12

    Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • Design of a 3-D Stacked Floating-point Goldschmidt Divider, IEEE International Conference on 3D System Integration (3DIC2015), 2015.08

    Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • A Cache Replacement Algorithm with Controlling Reference Counts, Proceedings of the Seventh International Conference on Information, 2015.11

    Jubee Tada

    Single Author

  • Effects of Stacking Granularity on 3D Stacked Floatingpoint Fused Multiply Add Units, Proceedings of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), 73-78, 2016.07

    Jubee Tada, Maiki Hosokawa, Ryusuke Egawa, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units, ACM SIGARCH Computer Architecture News, 44(4) 62-67, 2016.09

    Jubee Tada, Maiki Hosokawa, Ryusuke Egawa, Hiroaki Kobayashi

    Multiple Authorship (Only Japanese)

  • A Power-aware LLC Control Mechanism for the 3D-stacked Memory System, IEEE International Conference on 3D System Integration (3DIC2016), 2016.11

    Ryusuke Egawa, Wataru Uno, Masayuki Sato, Hiroaki Kobayashi, Jubee Tada

    Multiple Authorship (Only Japanese)

  • An Adaptive Demotion Policy for High-Associativity Caches, Proceedings of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017), USB 1-6, 2017.06

    Jubee Tada, Masayuki Sato, Ryusuke Egawa

    Multiple Authorship (Only Japanese)

  • A Cache Replacement Policy with Considering Global Fluctuations of Priority Values, Proceedings of Sixth International Symposium on Computing and Networking Workshops, 383-386, 2018.11

    Jubee Tada

    Single Author

  • An Adaptive Demotion Policy with considering Temporal Locality, Proceedings of Sixth International Symposium on Computing and Networking Workshops, 166-169, 2018.11

    Masahiro Hasegawa, Jubee Tada

    Multiple Authorship (Only Japanese)

  • A Cache Replacement Policy with Considering Global Fluctuations of Priority Values, International Journal of Networking and Computing, 9(2) 161-170, 2019.07

    Jubee Tada

    Single Author

  • A Design Scheme for 3-D Stacked CNN Accelerators, IEEE International Conference on 3D System Integration (3DIC2019), 2019.10

    Jubee Tada, Kazuto Takahashi, Ryusuke Egawa

    Multiple Authorship (Only Japanese)

  • A Cache Replacement Policy with Considering Fluctuation Patterns of Total Priority Value, Proceedings of Seventh International Symposium on Computing and Networking Workshops, 309-312, 2019.11

    Jubee Tada, Ryosuke Higashi

    Multiple Authorship (Only Japanese)

  • A Cache Replacement Policy with Considering Fluctuation Patterns of Total Priority Value, International Journal of Networking and Computing, 10(2) 200-212, 2020.07

    Jubee Tada, Ryosuke Higashi

    Multiple Authorship (Only Japanese)

  • An Implementation of a Grid Square Codes Generator on a RISC-V Processor, Proceedings of the 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW2020), 294-297, 2020.11

    Jubee Tada, Keiichi Sato

    Multiple Authorship (Only Japanese)

  • An Implementation of a World Grid Square Codes Generator on a RISC-V Processor, Proceedings of the 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW2021), 309-312, 2021.11

    Rei Watanabe, Jubee Tada, Keiichi Sato

    Multiple Authorship (Only Japanese)

  • An Implementation of a Grid Square Codes Generator on a RISC-V Processor, International Journal of Networking and Computing, 12(1) 204-217, 2022.01

    Jubee Tada, Keiichi Sato

    Multiple Authorship (Only Japanese)

  • An Implementation of a Pattern Matching Accelerator on a RISC-V Processor, Proceedings of the 2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW2022), 273-275, 2022.11

    Riku Takayama, Jubee Tada

    Multiple Authorship (Only Japanese)

  • An Implementation of an Instruction Controlled Cache Replacement Policy on a RISC-V Processor, 2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW), 172-178, 2023.11

    Riku Takayama, Jubee Tada

    Multiple Authorship (Only Japanese)

  • An Implementation of a Pattern-matching Accelerator on a RISC-V Processor, 122(60) 43-44, 2022.06

    Multiple Authorship (Only Japanese)

  • High Performance Hybrid Wave-Pipelined Adder Using Gain Based Delay Model, ICDV2010, 131-136, 2010.08

    Truong Tuoi, Jubee Tada, Gensuke Goto

    Multiple Authorship (Including Foreigners)

  • Reducing the Circuit Size of Multipliers, 信学技報, 106(314) 45-50, 2006.10

    Tan Jiunn Jong Edwin, Ryusuke Egawa, Jubee Tada, Kenichi Suzuki, Gensuke Goto, Tadao Nakamura

    Multiple Authorship (Including Foreigners)

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Grant-in-Aid for Scientific Research

  • Grant-in-Aid for Scientific Research(B)，2019.04 - 2021.03

  • Grant-in-Aid for Scientific Research(B)，2014.04 - 2017.03

  • Grant-in-Aid for Scientific Research(C)，2014.04 - 2017.03

  • Grant-in-Aid for Scientific Research(C)，2012.04 - 2015.03

  • Grant-in-Aid for Young Scientists(B)，2006.04 - 2008.03